Hardware

From the APC website:

The type of batteries used in APC's uninterruptible power supplies are sealed, nonspillable, maintenance-free, lead-acid batteries. The electrolyte is suspended in felt pads within the battery and therefore the batteries are spill-proof. The battery terminals are protected against short-circuit during transport. APC adheres to provision number A67 in the Material Safety Data Sheet (MSDS) for the batteries that are used. Since different batteries are used in different UPS systems, the MSDS sheets are not UPS model specific but rather battery specific. Any of the mentioned manufacturers could be used as almost any UPS battery. The battery manufacturer's name may be located on the battery itself. If it is not, the Back UPS, Smart UPS, Matrix, and Symmetra units generally use CSB or Panasonic batteries. B&B Battery, Power Battery, and Yuasa are used for larger UPS systems. Please find the MSDS sheets for the battery installed in your particular UPS below.

• BB-BATTERY_MSDS.pdf
• CSB_MSDS.doc
• PANASONIC_MSDS.pdf
• POWER_MSDS.pdf
• VISION_MSDS.pdf

In addition to caching reads from memory, the system is capable of caching writes to memory. The handling of the address bits and the cache lines, etc. is pretty similar to how this is done when the cache is read. However, there are two different ways that the cache can handle writes, and this is referred to as the "write policy" of the cache.

• Write-Back Cache: Also called "copy back" cache, this policy is "full" write caching of the system memory. When a write is made to system memory at a location that is currently cached, the new data is only written to the cache, not actually written to the system memory. Later, if another memory location needs to use the cache line where this data is stored, it is saved ("written back") to the system memory and then the line can be used by the new address.
• Write-Through Cache: With this method, every time the processor writes to a cached memory location, both the cache and the underlying memory location are updated. This is really sort of like "half caching" of writes; the data just written is in the cache in case it is needed to be read by the processor soon, but the write itself isn't actually cached because we still have to initiate a memory write operation each time.

Many caches that are capable of write-back operation can also be set to operate as write-through (not all however), but not generally the other way around.

Comparing the two policies, in general terms write-back provides better performance, but at the slight risk of memory integrity. Write-back caching saves the system from performing many unnecessary write cycles to the system RAM, which can lead to noticeably faster execution. However, when write-back caching is used, writes to cached memory locations are only placed in cache, and the RAM itself isn't actually updated until the cache line is booted out to make room for another address to use it.

As a result, at any given time, there can be a mismatch between many of the lines in the cache and the memory addresses that they correspond to. When this happens, the data in the memory is said to be "stale", since it doesn't have the fresh information yet that was only written to the cache. Memory used with a write-through cache can never be "stale" because the system memory is written at the same time that the cache is.

Normally, stale memory isn't a problem, because the cache controller keeps track of which locations in the cache have been changed and therefore which memory locations may be stale. This is done by using an extra single bit of memory, one per cache line, called the "dirty bit". Whenever a write is cached, this bit is set (made a 1) to tell the cache controller "when you decide to re-use this cache line for a different address, you need to write the current contents back to memory". This dirty bit is normally implemented by adding one extra bit to the tag RAM, instead of using a separate memory chip (to save cost).

However, the use of a write-back cache does entail the small possibility of data corruption if something were to happen before the "dirty" cache lines could be saved to memory. There aren't too many cases where this could happen, because both the memory and the cache are volatile (cleared when the machine is powered off).

On the other hand, consider a disk cache, where system memory is used to cache writes to the disk. Here, the memory is volatile but the disk is not. If a write-back cache is used here, you could have stale data on your disk compared to what is in memory. Then, if the power goes out, you lose everything that hadn't yet been written back to the disk, leading to possible corruption. For this reason, most disk caches allow programs to over-rule the write-back policy to ensure consistency between the cache (in memory) and disk. Disk utilities, for example, don't like write-back caching very much!

It is also possible with many caches to tell the controller "please write out to system memory all dirty cache lines, right now". This is done when it is necessary to make sure that the cache is in sync with the memory, and there is no stale data. This is sometimes called "flushing" the cache, and is especially common with disk caches, for the reason outlined in the previous paragraph.

The correct part number for the HP laserjet 1020 printer is C2612A. It is not listed on the box from Onyx.

In addition to the obvious benefits of longer maximum cable length than single-ended and a doubling of data throughput, there are a number of other benefits. LVD/MSE and single-ended offer some compatibility. The lower operating voltage of the LVD bus means lower power dissipation, so the differential drivers can be included on the LVD ASIC rather than having to mount them external to the chip. This results in smaller boards, less heat dissipation, higher reliability and lower cost. Also, manufacturers will no longer have to design and build devices with both single-ended and differential interfaces. This results in lower costs.

Multimode LVD and LVD/MSE (Multimode Single-Ended) are terms for the same interface. It is an implementation of SCSI that automatically switches between the LVD and the single-ended mode. When a single-ended device is connected to a multimode LVD/MSE bus, the entire bus switches to the single-ended mode. Otherwise LVD/MSE devices operate in the LVD mode.